bgb550 mirror biased transistor mmic never stop thinking. wireless silicon discretes p r e l i m i n a r y preliminary data sheet, bgb550, july 2001
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for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com bgb550 preliminary data sheet revision history: 2001-07-31 preliminary previous version: 2001-01-19 page subjects (major changes since last revision) all pages change from word to framemaker - complete reworked we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
preliminary data sheet 4 2001-07-31 esd: electrostatic discharge sensitive device, observe handling precaution! type package marking chip bgb550 sct595 mds t0529 mirror biased transistor bgb550 preliminary vpw05980 1 2 3 5 4 b, 1 e, 2, 5 c, 4 bias, 3 features ideal for driver appliciations small sct595 package open collector output typical supply voltage: 1.4-4.3v current easy adjustable by an external resistor sieget?-45 technology description the bgb 550 is a silicon mirror biased rf transistor. the rf transistor is biased simply by adding an external resistor to the bias pin and an inductor as rf choke. there is no voltage drop at the collector. the mirror transistors are matched with a ratio of 1:14. if a higher degree of current stabilisation over supply voltage is needed a current source can be added without voltage drop at the collector. 4, c 5, e b ,1 e ,2 bias ,3
bgb550 preliminary data sheet 5 2001-07-31 preliminary maximum ratings notes: for detailed symbol description refer to figure 1. 1) t s is measured on the emitter lead at the soldering point to the pcb parameter symbol value unit maximum collector-emitter voltage v ce 4.5 v maximum collector current i c 350 ma maximum bias current i bias 25 ma maximum emitter-base voltage v eb 1.5 v maximum base current i b 40 ma total power dissipation, t s < 75 c 1) p tot 1000 mw junction temperature t j 150 c operating temperature range t op -65 ... +150 c storage temperature range t stg -65 ... +150 c thermal resistance: junction-soldering point r th js 75 k/w fig. 1: symbol definition bias,3 c,3 b,1 e,2 v eb i bias i c v ce i b
bgb550 preliminary data sheet 6 2001-07-31 preliminary 2 3 5 4 top view rfin rfout b e c bias 1 e v cc bias-t bias-t r bias reference plane reference plane v bias electrical characteristics at t a =25c (measured in test circuit specified in fig. 2) parameter symbol min. typ. max. unit maximum stable power gain f=0.9ghz v cc =2v, i c =100ma f=1.8ghz g ms 22 16 db insertion power gain f=0.9ghz v cc =2v, i c =100ma f=1.8ghz |s 21 | 2 17 11 db insertion loss f=0.9ghz v cc =2v, i c =0ma f=1.8ghz il -12.5 -13 db noise figure (z s =z sopt ) i c =10ma v cc =2v, f=1.8ghz i c =50ma f opt 1.2 1.5 db output power at 1db gain compression v cc =2v, i c =100ma, f=1.8ghz z l =z lopt z l =50 ? p -1db 19 15 dbm output third order intercept point v cc =2v, i c =100ma, f=1.8ghz z l/s =z l/sopt z l/s =50 ? oip 3 28 25 dbm collector-base capacitance v cb =2v, f=1mhz c cb 0.6 pf current ratio i c /(i bias + i b ) i bias + i b =5ma, v cc =2v cr 10 14 17 fig. 2: test circuit for electrical characteristics and s-parameter
bgb550 preliminary data sheet 7 2001-07-31 preliminary power gain g ms , g ma = f(i c ) v cc = 2.0v 0 50 100 150 200 250 300 350 0 5 10 15 20 25 30 35 40 i c [ma] g ms , g ma [db] 0.3 ghz 0.9 ghz 1.8 ghz 2.4 ghz power gain |s 21 | 2 , g ms , g ma = f(f) v cc = 2.0v; i c = 0.10a 0 1 2 3 4 5 6 0 5 10 15 20 25 30 35 40 45 50 frequency [ghz] |s 21 | 2 , g ms , g ma [db] |s 21 | 2 g ms g ma s-parameter t a =25c,v ce =2v, i c =100ma (measured in test circuit specified in fig. 2) f s11 s11 s21 s21 s12 s12 s22 s22 [ghz] ma g an g ma g an g ma g an g ma g an g 0.1 0.6217 -150.7 57.9230 123.0 0.0112 50.7 0.6959 -97.7 0.2 0.7181 -166.6 33.3990 104.4 0.0150 48.1 0.6248 -134.5 0.4 0.7497 -179.3 17.2680 89.4 0.0210 52.6 0.5988 -161.2 0.6 0.7630 173.3 11.4480 81.0 0.0272 55.7 0.6018 -173.1 0.8 0.7682 167.3 8.4390 74.4 0.0342 56.3 0.6070 179.0 1.0 0.7747 162.3 6.6270 69.1 0.0410 55.4 0.6171 172.8 1.2 0.7807 157.9 5.4350 64.3 0.0473 54.6 0.6223 167.7 1.4 0.7874 153.7 4.5780 59.9 0.0545 52.6 0.6323 163.0 1.6 0.7912 150.0 3.9570 55.7 0.0613 50.3 0.6383 159.0 1.8 0.7985 146.2 3.4780 51.6 0.0682 47.9 0.6482 155.0 2.0 0.8017 142.8 3.0980 47.6 0.0747 45.7 0.6523 151.6 2.4 0.8079 136.3 2.5350 40.0 0.0875 40.5 0.6638 145.0 3.0 0.8117 126.7 1.9930 28.9 0.1081 32.3 0.6738 135.2 4.0 0.8124 109.0 1.4660 8.8 0.1440 14.8 0.6947 118.2 5.0 0.8059 90.9 1.0920 -11.8 0.1708 -7.0 0.6902 99.5 6.0 0.8087 79.2 0.7820 -31.9 0.1750 -37.8 0.6612 89.0
bgb550 preliminary data sheet 8 2001-07-31 preliminary reverse isolation |s 12 | = f(f) v cc = 2.0v; i c = 0.10a 0 1 2 3 4 5 6 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 frequency [ghz] |s 12 | [db] stability k, b 1 = f(f) v cc = 2.0v; i c = 0.10a 0 1 2 3 4 5 6 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 frequency [ghz] k, b 1 k b1 matching |s 11 |, |s 22 | = f(f) v cc = 2.0v; i c = 0.10a f = 0.01ghz ? 6ghz 1 0.1 0.2 0.3 0.4 0.5 2 1.5 3 4 5 0 1 ? 1 1.5 ? 1.5 2 ? 2 3 ? 3 4 ? 4 5 ? 5 10 ? 10 0.5 ? 0.5 0.1 ? 0.1 0.2 ? 0.2 0.3 ? 0.3 0.4 ? 0.4 s 11 s 22 matching |s 11 |, |s 22 | = f(f) v cc = 2.0v; i c = 0.10a 0 1 2 3 4 5 6 ? 10 ? 9 ? 8 ? 7 ? 6 ? 5 ? 4 ? 3 ? 2 ? 1 0 frequency [ghz] |s 11 |, |s 22 | [db] s 11 s 22
bgb550 preliminary data sheet 9 2001-07-31 preliminary acc. to +0.2 1.9 0.6 -0.05 +0.1 +0.1 -0.05 0.3 b a 0.25 m b 1.1 max 2.6 max 10max 0.1 max a m 0.20 2.9 0.2 1.6 0.1 din 6784 (2.2) (0.3) 1.2 -0.05 +0.1 0.95 -0.06 +0.1 0.15 10max 0.25 min (0.4) 1) (0.23) 1) (0.13) 1) contour of slot depends on profile of gull-wing lead form b ,1 e, 2, 5 rfout bias,3 v cc c1=1nf c2=150pf l1=100nh rbias rfc c ,4 rfin this proposal demonstrates how to use the bgb550 as a self-biased transistor. as for a discrete transistor matching circuits have to be applied. the rfc circuit (e.g. an inductor) can be used to improve the input match. typical application package outline i c =14*i bias fig. 3: typical application circuit
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